The present invention relates to a data transmission control device, and more particularly to a data transmission control device suited for controlling the transmission of a large amount of data between two memory means.
One of the serious problems with respect to use of an external memory in of a computer system is that data transfer with the external memory is performed at low speed. The use of a semiconductor memory as the external memory may be effective to solve the above problem. However, if data is transferred between semiconductor memories through an input/output processor, the transfer speed will be limited by the transfer capability of the input/output processor. In more detail, the input/output processor reads out data from a specified external memory, for example, byte by byte, irrespective of the access unit thereof, and writes the data in another external memory in accordance with the access unit thereof. That is, when data in the high-speed memory is transferred to another memory, the speed of data transfer is determined by the transfer speed of the input/output processor. Accordingly, in the case where data transmission between high-speed semiconductor memories is controlled by an input/output processor, it is impossible to fully utilize the high-speed capability of each semiconductor memory.
In some cases, however, data transfer between semiconductor memories is carried out without using any input/output processor. The data transfer between a main memory and a buffer memory is an example of such data transfer. The buffer memory is required to rapidly respond to each of the data read-out requests from a central processor. The data stored in the buffer memory represents copies of data which are scattered in the main memory, and therefore there is little probability that a plurality of transfer unit data (namely, a plurality of unit data each indicating the, access unit of the buffer memory) in the buffer memory will be processed together. Thus, it is required to transfer only one transfer unit data at a time, and the transfer unit data can be transferred at high speed. However, a data transmission control device used in this case receives only an instruction for one transfer unit data, from the central processor, and does not have a function of decomposing an original instruction for transferring a large amount of data into a plurality of transfer instructions each requiring the transfer of unit data, which is the processing unit of the data transmission control device. Accordingly, the above system is not suited for the transmission of a large amount of data. However, if it is desired to transmit a large amount of data by the above system, it will be required to decompose the original instruction for a large amount of data by the central processor itself into a plurality of transfer instructions each requiring the transfer of unit data, and thus a heavy burden will be cast on the central processor.